The invention relates to a method of manufacturing a semiconductor device of the hetero-junction bipolar transistor type having a planar structure, this method comprising at least the step of manufacturing a structure comprising successively at least one collector layer of a binary material of a first conductivity type, a base layer of a binary material of the second conductivity type opposite to the first type, an emitter layer of ternary material of the first conductivity type and a binary highly doped contact layer of the first conductivity type.
The invention is used in the manufacture of integrated circuits on materials of the III-V group and especially on gallium aresenide including hetero-junction bipolar transistors.
A hetero-junction bipolar transistor having a planar structure is already known from the publication entitled "A Fully Planar Hetero-junction Bipolar Transistor" by John W. Tully et alii in "I.E.E.E. Electron Device Letters", Vol. EDL 7, No. 11, November 1986, pp. 615-617.
This document describes a transistor formed on a semiconductor substrate of the n.sup.+ conductivity type. This transistor comprises a first layer of GaAs of the n.sup.+ type, a second layer of GaAs of the n-type and a base layer of the p.sup.+ type formed by localized implantation in the upper part of the layer of n-type GaAs.
This transistor further comprises two upper layers, the first layer of FaAlAs of the n-type to form the emitter and the second layer of GaAs of the n.sup.+ type to permit the connection of the contacts. The base regions are constituted by p.sup.+ islands connecting the base contacts to an implanted p.sup.+ layer.
The method of manufacturing this transistor begins with the epitaxial growth of the n.sup.+ and n collector layers by the so-called MOCVD method. The base region is defined by a photoresist mask and is implanted selectively by means of Zn.sup.+ ions. After elimination of the photoresist layer, the substrate is reinserted into the MOCVD reactor for an annealing treatment at high temperature. This operation is immediately followed by the growth of the n-type emitter layer of GaAlAs and the n.sup.+ type contact layer of GaAs. The emitter layer having the composition Ga.sub.1-x Al.sub.x As has a gradient of the concentration x of Al. In the first 50 nm, the concentration x lies between 0 and 0.30. Subsequently, the remaining part of the emitter layer is formed with x =0.30 of Al. Subsequently, the device is covered by SiO.sub.2 and then by a layer of Al having each a thickness of 400 nm. The base contacts are defined by photolithography and the aluminum is chemically etched, whereupon the layer of SiO.sub.2 is etched by plasma. This method results in a stronger etching of SiO.sub.2 than that of Al, as a result of which a projection is obtained above SiO.sub.2. This method later serves for the "lift-off" of the aluminum. The upper layer of GaAs is thus uncovered and Zn.sup. + ions are implanted in the openings of Al/SiO.sub.2. Subsequently, a metal apt to form a p-type contact, such as Mo/Cr, is evaporated. At this stage of the method, the aluminum is eliminated chemically, which permits of eliminating the excess of Mo/Cr. After the "lift-off", the sample is annealed at high temperature to activate the p.sup.+ implantation. Finally, the emitter and collector contacts defined by photolithography are formed simultaneously by means of metallization of AuGe/Ni/Au the excess metal is eliminated and its contacts are annealed.
In this known method, the emitter and collector metallizations are "simply aligned" with respect to the base metallization. This type of alignment leads to a precision of hardly more than 1 .mu.m. This results in that the distances between the emitter and base metallizations and the distances between the collector and base metallizations are at least equal to 1 .mu.m. In these conditions, the transistors have dimensions too large to be compatible with the performances required for the envisaged application.